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features ? 8-bit microcontroller compatible with 8051 products ? enhanced 8051 architecture ? single clock cycle per byte fetch ? 12 clock per machine cy cle compatibility mode ? up to 20 mips throughput at 20 mhz clock frequency ? fully static operation: 0 hz to 20 mhz ? on-chip 2-cycle hardware multiplier ? 16x16 multiply?accumulate unit ? 256 x 8 internal ram ? on-chip 2kb expanded ram (eram) ? software selectable size (0, 256, 512, 768, 1024, 1792, 2048 bytes) ? dual data pointers ? 4-level interrupt priority ? nonvolatile program and data memory ? 64kb of in-system programmable (isp) flash program memory ? 4kb of eeprom (at89lp51ed2/id2 only) ? 512-byte user signature array ? endurance: 10,000 write/erase cycles ? serial interface for program downloading ? 2kb boot rom contains low level flash programming routines and a default serial bootloader ? peripheral features ? three 16-bit enhanced timer/counters ? seven 8-bit pwm outputs ? 16-bit programmable counter array ? high speed output , compare/capture ? pulse width modulation, watchdog timer capabilities ? enhanced uart with automatic ad dress recognition and framing error detection ? enhanced master/slave spi with double-buffered send/receive ? two wire interface 400k bit/s ? programmable watchdog timer with software reset ? 8 general-purpose interrupt and keyboard interface pins ? special microcontroller features ? dual oscillator support: crystal, 32 kh z crystal, 8 mhz inte rnal (at89lp51id2) ? two-wire on-chip debug interface ? brown-out detection and power-on reset with power-off flag ? selectable polarity external reset pin ? low power idle and power-down modes ? interrupt recovery from power-down mode ? 8-bit clock prescaler ? i/o and packages ? up to 40 programmable i/o lines ? green (pb/halide-free) plcc 44, vqfp44, qfn44, pdip40 ? configurable i/o modes ? quasi-bidirectional (80c51 st yle), input-only (tristate) ? push-pull cmos output, open-drain ? operating conditions ? 2.4v to 5.5v v cc voltage range ?-40 c to 85c temperature range ? 0 to 20 mhz @ 2.4v?5.5v (single-cycle) 8-bit flash microcontroller with 64kb program memory at89lp51rd2 at89lp51ed2 at89lp51id2 preliminary summary 3714as?micro?7/11
2 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 1. pin configurations 1.1 44-lead vqfp 1.2 44-lead plcc 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 (?mo s i/cex2/mi s o) p1.5 (?mi s o/cex 3 / s ck) p1.6 (? s ck/cex4/mo s i) p1.7 (dcl) r s t (rxd) p 3 .0 ( s da) p4.1 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.0 ( s cl) p4.4 (ale) p4.5 (p s en) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) p1.4 (cex1/ ss ?) p1. 3 (cex0) p1.2 (eci) p1.1 (t2 ex/ ss ) p1.0 (t2/xtal1b?) p4.2 (xtal2b?) vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 v ss (dda) p4. 3 (a8) p2.0 (a9) p2.1 (dac-/a10) p2.2 (dac+/a11) p2. 3 (ain0/a12) p2.4 ? s pi in remap mode ? at89lp51id2 only 7 8 9 10 11 12 1 3 14 15 16 17 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 (?mo s i/cex2/mi s o) p1.5 (?mi s o/cex 3 / s ck) p1.6 (? s ck/cex4/mo s i) p1.7 (dcl) r s t (rxd) p 3 .0 ( s da) p4.1 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.0 ( s cl) p4.4 (ale) p4.5 (p s en) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) 6 5 4 3 2 1 44 4 3 42 41 40 18 19 20 21 22 2 3 24 25 26 27 28 (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 v ss (dda) p4. 3 (a8) p2.0 (a9) p2.1 (dac-/a10) p2.2 (dac+/a11) p2. 3 (ain0/a12) p2.4 p1.4 (cex1/ ss ?) p1. 3 (cex0) p1.2 (eci) p1.1 (t2 ex/ ss ) p1.0 (t2/xtal1b?) p4.2 (xtal2b?) vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) ? s pi in remap mode ? at89lp51id2 only 1.3 44-pad vqfn/qfn/mlf 1.4 40-pin pdip 1 2 3 4 5 6 7 8 9 10 11 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 44 4 3 42 41 40 3 9 3 8 3 7 3 6 3 5 3 4 12 1 3 14 15 16 17 18 19 20 21 22 bottom pad should be soldered to ground note: ? s pi in remap mode ? at89lp51id2 only (?mo s i/cex2/mi s o) p1.5 (?mi s o/cex 3 / s ck) p1.6 (? s ck/cex4/mo s i) p1.7 (dcl) r s t (rxd) p 3 .0 ( s da) p4.1 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.0 ( s cl) p4.4 (ale) p4.5 (p s en) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) p1.4 (cex1/ ss ?) p1. 3 (cex0) p1.2 (eci) p1.1 (t2 ex/ ss ) p1.0 (t2/xtal1b?) p4.2 (xtal2b?) vdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 gnd (dda) p4. 3 (a8) p2.0 (a9) p2.1 (da-/a10) p2.2 (da+/a11) p2. 3 (ain0/a12) p2.4 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 40 3 9 3 8 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 28 27 26 25 24 2 3 22 21 (t2) p1.0 ( ss /t2ex) p1.1 (eci) p1.2 (cex0) p1. 3 (? ss /cex1) p1.4 (?mo s i/cex2/mi s o) p1.5 (?mi s o/cex 3 / s cl) p1.6 (? s ck/cex4/mo s i) p1.7 r s t (rxd) p 3 .0 (txd) p 3 .1 (int0) p 3 .2 (int1) p 3 . 3 (t0) p 3 .4 (t1) p 3 .5 (wr) p 3 .6 (rd) p 3 .7 (xtal2a) p4.7 (xtal1a) p4.6 gnd vdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0. 3 (ad 3 ) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) pol p4.4 (ale) p4.5 (p s en) p2.7 (a15/ain 3 ) p2.6 (a14/ain2) p2.5 (a1 3 /ain1) p2.4 (a12/ain0) p2. 3 (a11/dac+) p2.2 (a10/dac-) p2.1 (a9) p2.0 (a8) ?spi in remap mode
3 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 1.5 pin description table 1-1. atmel at 8 9lp51rd2/ed2/id2 pin de s cription pin number symbol type description vqfp vqfn plcc (1) pdip 176p1.5 i/o i/o i/o i/o p1.5 : u s er-config u r ab le i/o port 1 b it 5. miso : spi m as ter-in/ s l a ve-o u t. when config u red as m as ter, thi s pin i s a n inp u t. when config u red as s l a ve, thi s pin i s a n o u tp u t. mosi : spi m as ter-o u t/ s l a ve-in (rem a p mode). when config u red as m as ter, thi s pin i s a n o u tp u t. when config u red as s l a ve, thi s pin i s a n inp u t. d u ring in-sy s tem progr a mming, thi s pin i s a n inp u t. cex2 : c a pt u re/comp a re extern a l i/o for pca mod u le 2. 2 8 7p1.6 i/o i/o i/o i/o p1.6 : u s er-config u r ab le i/o port 1 b it 6. sck : spi clock. when config u red as m as ter, thi s pin i s a n o u tp u t. when config u red as s l a ve, thi s pin i s a n inp u t. miso : spi m as ter-in/ s l a ve-o u t (rem a p mode). when config u red as m as ter, thi s pin i s a n inp u t. when config u red as s l a ve, thi s pin i s a n o u tp u t. d u ring in-sy s tem progr a mming, thi s pin i s a n o u tp u t. cex3 : c a pt u re/comp a re extern a l i/o for pca mod u le 3. 39 8 p1.7 i/o i/o i/o i/o p1.7 : u s er-config u r ab le i/o port 1 b it 7. mosi : spi m as ter-o u t/ s l a ve-in. when config u red as m as ter, thi s pin i s a n o u tp u t. when config u red as s l a ve, thi s pin i s a n inp u t. sck : spi clock (rem a p mode). when config u red as m as ter, thi s pin i s a n o u tp u t. when config u red as s l a ve, thi s pin i s a n inp u t. d u ring in-sy s tem progr a mming, thi s pin i s a n inp u t. cex4 : c a pt u re/comp a re extern a l i/o for pca mod u le 4. 4109 rst i/o i rst : extern a l re s et inp u t (re s et pol a rity depend s on pol pin). the rst pin c a n o u tp u t a p u l s e when the intern a l w a tchdog re s et or por i s a ctive. dcl : seri a l de bu g clock inp u t for on-chip de bu g interf a ce when ocd i s en ab led. 51110p3.0 i/o i p3.0 : u s er-config u r ab le i/o port 3 b it 0. rxd : seri a l port receiver inp u t. 612 p4.1 i/o i/o p4.1 : u s er-config u r ab le i/o port 4 b it 1. sda : twi b idirection a l seri a l d a t a line. 71311p3.1 i/o o p3.1 : u s er-config u r ab le i/o port 3 b it 1. txd : seri a l port tr a n s mitter o u tp u t. 8 14 12 p3.2 i/o i p3.2 : u s er-config u r ab le i/o port 3 b it 2. int0 : extern a l interr u pt 0 inp u t or timer 0 g a te inp u t. 91513p3.3 i/o i p3.3 : u s er-config u r ab le i/o port 3 b it 3. int1 : extern a l interr u pt 1 inp u t or timer 1 g a te inp u t 10 16 14 p3.4 i/o i/o p3.4 : u s er-config u r ab le i/o port 3 b it 4. t1 : timer/co u nter 0 extern a l inp u t or o u tp u t. 11 17 15 p3.5 i/o i/o p3.5 : u s er-config u r ab le i/o port 3 b it 5. t1 : timer/co u nter 1 extern a l inp u t or o u tp u t. 12 1 8 16 p3.6 i/o o p3.6 : u s er-config u r ab le i/o port 3 b it 6. wr : extern a l memory interf a ce write stro b e ( a ctive-low). 13 19 17 p3.7 i/o o p3.7 : u s er-config u r ab le i/o port 3 b it 7. rd : extern a l memory interf a ce re a d stro b e ( a ctive-low). 14 20 1 8 p4.7 i/o o p4.7 : u s er-config u r ab le i/o port 4 b it 7. xtal2a : o u tp u t from inverting o s cill a tor a mplifier a. it m a y b e us ed as a port pin if the intern a l rc o s cill a tor or extern a l clock i s s elected as the clock s o u rce a. 15 21 19 p4.6 i/o i p4.6 : u s er-config u r ab le i/o port 4 b it 6. xtal1a : inp u t to the inverting o s cill a tor a mplifier a a nd intern a l clock gener a tion circ u it s . it m a y b e us ed as a port pin if the intern a l rc o s cill a tor i s s elected as the clock s o u rce a.
4 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 16 22 20 gnd i gro u nd 17 23 p4.3 i/o i/o p4.3 : u s er-config u r ab le i/o port 4 b it 3. dda : bidirection a l de bu g d a t a line for the on-chip de bu g interf a ce when ocd i s en ab led. 1 8 24 21 p2.0 i/o o p2.0 : u s er-config u r ab le i/o port 2 b it 0. a8 : extern a l memory interf a ce addre ss b it 8 . 19 25 22 p2.1 i/o o p2.1 : u s er-config u r ab le i/o port 2 b it 1. a9 : extern a l memory interf a ce addre ss b it 9. 20 26 23 p2.1 i/o o o p2.2 : u s er-config u r ab le i/o port 2 b it 2. da- : dac neg a tive differenti a l o u tp u t. a10 : extern a l memory interf a ce addre ss b it 10. 21 27 24 p2.3 i/o o o p2.3 : u s er-config u r ab le i/o port 2 b it 3. da+- : dac po s itive differenti a l o u tp u t. a11 : extern a l memory interf a ce addre ss b it 11. 22 2 8 25 p2.4 i/o i o p2.4 : u s er-config u r ab le i/o port 2 b it 5. ain0 : an a log comp a r a tor inp u t 0. a12 : extern a l memory interf a ce addre ss b it 12. 23 29 26 p2.5 i/o i o p2.5 : u s er-config u r ab le i/o port 2 b it 5. ain1 : an a log comp a r a tor inp u t 1. a13 : extern a l memory interf a ce addre ss b it 13. 24 30 27 p2.6 i/o i o p2.6 : u s er-config u r ab le i/o port 2 b it 6. ain2 : an a log comp a r a tor inp u t 2. a14 : extern a l memory interf a ce addre ss b it 14. 25 31 2 8 p2.7 i/o i o p2.7 : u s er-config u r ab le i/o port 2 b it 7. ain3 : an a log comp a r a tor inp u t 3. a15 : extern a l memory interf a ce addre ss b it 15. 26 32 29 p4.5 i/o o p4.5 : u s er-config u r ab le i/o port 4 b it 5. psen : extern a l memory interf a ce progr a m store en ab le ( a ctive-low). 27 33 30 p4.4 i/o i/o p4.4 : u s er-config u r ab le i/o port 4 b it 4. ale : extern a l memory interf a ce addre ss l a tch en ab le. 2 8 34 p4.0 i/o p4.0 : u s er-config u r ab le i/o port 4 b it 0. scl : twi seri a l clock line. thi s line i s a n o u tp u t in m a ter mode a nd a n inp u t in s l a ve mode. 29 35 31 pol i pol : re s et pol a rity 30 36 32 p0.7 i/o i/o p0.7 : u s er-config u r ab le i/o port 0 b it 7. ad7 : extern a l memory interf a ce addre ss /d a t a b it 7. 31 37 33 p0.6 i/o i/o i p0.6 : u s er-config u r ab le i/o port 0 b it 6. ad6 : extern a l memory interf a ce addre ss /d a t a b it 6. adc6 : adc a n a log inp u t 6. 32 3 8 34 p0.5 i/o i/o i p0.5 : u s er-config u r ab le i/o port 0 b it 5. ad5 : extern a l memory interf a ce addre ss /d a t a b it 5. adc5 : adc a n a log inp u t 5. 33 39 35 p0.4 i/o i/o i p0.4 : u s er-config u r ab le i/o port 0 b it 4. ad4 : extern a l memory interf a ce addre ss /d a t a b it 4. adc4 : adc a n a log inp u t 4. 34 40 36 p0.3 i/o i/o i p0.3 : u s er-config u r ab le i/o port 0 b it 3. ad3 : extern a l memory interf a ce addre ss /d a t a b it 3. adc3 : adc a n a log inp u t 3. table 1-1. atmel at 8 9lp51rd2/ed2/id2 pin de s cription pin number symbol type description vqfp vqfn plcc (1) pdip
5 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary note: 1. the at 8 9lp51id2 i s not a v a il ab le in the pdip p a ck a ge. 2. overview the atmel ? at 8 9lp51rd2/ed2/id2 i s a low-power, high-perform a nce cmos 8 - b it 8 051 micro- controller with 64kb of in-sy s tem progr a mm ab le fl as h progr a m memory. the at 8 9lp51ed2 a nd at 8 9lp51id2 provide a n a ddition a l 4kb of eeprom for nonvol a tile d a t a s tor a ge. the device s a re m a n u f a ct u red us ing atmel' s high-den s ity nonvol a tile memory technology a nd a re comp a ti b le with the ind us try- s t a nd a rd 8 0c51 in s tr u ction s et. the at 8 9lp51rd2/ed2/id2 i s bu ilt a ro u nd a n enh a nced cpu core th a t c a n fetch a s ingle b yte from memory every clock cycle. in the cl ass ic 8 051 a rchitect u re, e a ch fetch req u ire s 6 clock cycle s , forcing in s tr u ction s to exec u te in 12, 24 or 4 8 clock cycle s . in the at 8 9lp51rd2/ed2/id2 cpu, s t a nd a rd in s tr u ction s need only one to fo u r clock cycle s providing s ix to twelve time s more thro u ghp u t th a n the s t a nd a rd 8 051. seventy percent of in s tr u ction s need only as m a ny clock cycle s as they h a ve b yte s to exec u te, a nd mo s t of the rem a ining in s tr u ction s req u ire only one a ddition a l clock. the enh a nced cpu core i s c a p ab le of 20 mips thro u ghp u t where as the cl ass ic 8 051 cpu c a n deliver only 4 mips a t the sa me c u rrent con- su mption. conver s ely, a t the sa me thro u ghp u t as the cl ass ic 8 051, the new cpu core r u n s a t a m u ch lower s peed a nd there b y gre a tly red u cing power con su mption a nd emi. the 35 41 37 p0.2 i/o i/o i p0.2 : u s er-config u r ab le i/o port 0 b it 2. ad2 : extern a l memory interf a ce addre ss /d a t a b it 2. adc2 : adc a n a log inp u t 2. 36 42 3 8 p0.1 i/o i/o i p0.1 : u s er-config u r ab le i/o port 0 b it 1. ad1 : extern a l memory interf a ce addre ss /d a t a b it 1. adc1 : adc a n a log inp u t 1. 37 43 39 p0.0 i/o i/o i p0.0 : u s er-config u r ab le i/o port 0 b it 0. ad0 : extern a l memory interf a ce addre ss /d a t a b it 0. adc0 : adc a n a log inp u t 0. 3 8 44 40 vdd i s u pply volt a ge 39 1 p4.2 i/o p4.2 : u s er-config u r ab le i/o port 4 b it 2. xtal2b : o u tp u t from low-freq u ency inverting o s cill a tor a mplifier b (at 8 9lp51id2 only). it m a y b e us ed as a port pin if the intern a l rc o s cill a tor or extern a l clock i s s elected as the clock s o u rce. 40 2 1 p1.0 i/o i/o p1.0 : u s er-config u r ab le i/o port 1 b it 0. t2 : timer 2 extern a l inp u t or clock o u tp u t. xtal1b : inp u t to the low-freq u ency inverting o s cill a tor a mplifier b a nd intern a l clock gener a tion circ u it s . it m a y b e us ed as a port pin if the intern a l rc o s cill a tor i s s elected as the clock s o u rce. 41 3 2 p1.1 i/o i i p1.1 : u s er-config u r ab le i/o port 1 b it 1. t2ex : timer 2 extern a l c a pt u re/relo a d inp u t. ss : spi sl a ve-select. 42 4 3 p1.2 i/o p1.2 : u s er-config u r ab le i/o port 1 b it 2. 43 5 4 p1.3 i/o i/o p1.3 : u s er-config u r ab le i/o port 1 b it 3. cex0 : c a pt u re/comp a re extern a l i/o for pca mod u le 0. 44 6 5 p1.4 i/o i i/o p1.4 : u s er-config u r ab le i/o port 1 b it 4. ss : spi sl a ve-select (rem a p mode). thi s pin i s a n inp u t for in-sy s tem progr a mming cex1 : c a pt u re/comp a re extern a l i/o for pca mod u le 1. table 1-1. atmel at 8 9lp51rd2/ed2/id2 pin de s cription pin number symbol type description vqfp vqfn plcc (1) pdip
6 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary at 8 9lp51rd2/ed2/id2 a l s o incl u de s a comp a ti b ility mode th a t will en ab le cl ass ic 12 clock per m a chine cycle oper a tion for tr u e timing comp a ti b ility with the atmel at 8 9c51rd2/ed2. the at 8 9lp51rd2/ed2/id2 ret a in s a ll of the s t a nd a rd fe a t u re s of the at 8 9c51rd2/ed2, incl u ding: 64kb of in-sy s tem progr a mm ab le fl as h progr a m memory, 4kb of eeprom (at 8 9lp51ed2/id2 only), 256 b yte s of ram, 2kb of exp a nded ram, u p to 40 i/o line s , three 16- b it timer/co u nter s , a progr a mm ab le co u nter arr a y, a progr a mm ab le h a rdw a re w a tchdog timer, a key b o a rd interf a ce, a f u ll-d u plex enh a nced s eri a l port, a s eri a l peripher a l interf a ce (spi), on-chip cry s t a l o s cill a tor, a nd a fo u r-level, ten-vector interr u pt s y s tem. a b lock di a gr a m i s s hown in fig u re 2-1 . in a ddition, the atmel ? at 8 9lp51rd2/ed2/id2 provide s a two-wire interf a ce (twi) for u p to 400kb/ s s eri a l tr a n s fer; a 10- b it, 8 -ch a nnel an a log-to-digit a l converter (adc) with temper a t u re s en s or a nd digit a l-to- a n a log (dac) mode; two a n a log comp a r a tor s ; a n 8 mhz intern a l o s cill a tor; a nd more on-chip d a t a memory th a n the atmel at 8 9c51rd2/ed2 (4kb v s . 2kb eeprom a nd 204 8 v s . 1792 b yte s eram). some s t a nd a rd fe a t u re s on the at 8 9lp51rd2/ed2/id2 a re enh a nced with new mode s or oper- a tion s . mode 0 of timer 0 or timer 1 a ct s as a v a ri ab le 9?16 b it timer/co u nter a nd mode 1 a ct s as a 16- b it au to-relo a d timer/co u nter. in a ddition, e a ch timer/co u nter m a y independently drive a n 8 - b it preci s ion p u l s e width mod u l a tion o u tp u t. mode 0 ( s ynchrono us mode) of the s eri a l port a llow s flexi b ility in the ph as e/pol a rity rel a tion s hip b etween clock a nd d a t a . the i/o port s of the at 8 9lp51rd2/ed2/id2 c a n b e independently config u red in one of fo u r oper a ting mode s . in q uas i- b idirection a l mode, the port s oper a te as in the cl ass ic 8 051. in inp u t- only mode, the port s a re tri s t a ted. p us h-p u ll o u tp u t mode provide s f u ll cmos driver s a nd open- dr a in mode provide s j us t a p u ll-down. unlike other 8 051 s , thi s a llow s port 0 to oper a te with on- chip p u ll- u p s if de s ired. the at 8 9lp51rd2/ed2/id2 incl u de s a n on-chip de bu g (ocd) interf a ce th a t a llow s re a d-mod- ify-write c a p ab ilitie s of the s y s tem s t a te a nd progr a m flow control, a nd progr a mming of the intern a l memorie s . the on-chip fl as h a nd eeprom m a y a l s o b e progr a mmed thro u gh the uart- bas ed b ootlo a der or the spi- bas ed in-sy s tem progr a mming interf a ce (isp). the twi a nd ocd fe a t u re s a re not a v a il ab le on the pdip p a ck a ge. the at 8 9lp51id2 i s a l s o not a v a il ab le in pdip. the fe a t u re s of the at 8 9lp51rd2/ed2/id2 m a ke it a powerf u l choice for a pplic a tion s th a t need p u l s e width mod u l a tion, high s peed i/o, a nd co u nting c a p ab ilitie s su ch as a l a rm s , motor control, corded phone s , a nd s m a rt c a rd re a der s .
7 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 2.1 block diagram figure 2-1. atmel at 8 9lp51rd2/ed2/id2 block di a gr a m 2.2 system configuration the at 8 9lp51rd2/ed2/id2 su pport s s ever a l s y s tem config u r a tion option s . nonvol a tile option s a re s et thro u gh us er f us e s th a t m us t b e progr a mmed thro u gh the fl as h progr a mming interf a ce. vol a tile option s a re controlled b y s oftw a re thro u gh individ ua l b it s of s peci a l f u nction regi s ter s (sfr s ). the at 8 9lp51rd2/ed2/id2 m us t b e properly config u red b efore correct oper a tion c a n occ u r. 2.2.1 fuse options t ab le 2-1 li s t s the f us i b le option s for the at 8 9lp51rd2/ed2/id2. the s e option s m a int a in their s t a te even when the device i s powered off. some m a y b e ch a nged thro u gh the fl as h api bu t other s c a n only b e ch a nged with a n extern a l device progr a mmer. for more inform a tion, s ee the d a t as heet. flash code 64kb port 2 configurable i/o port 1 configurable i/o uart s pi timer 0 timer 1 watchdog timer crystal or resonator eeprom 4kb (at89lp51ed2/id2) port 4 configurable i/o port 3 configurable i/o timer 2 port 0 configurable i/o ram 256 bytes xram interface 8051 s ingle cycle cpu with 12-cycle compatiblity por bod dual data pointers multiply accumulate (16 x 16) eram 2kb keyboard interface pca boot rom 2kb on-chip debug internal 8 mhz rc oscillator configurable oscillator a 10-bit adc/dac twi 7 dual analog comparators crystal or resonator configurable oscillator b (at89lp51id2)
8 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 2.2.2 software options t ab le 2-2 li s t s s ome import a nt s oftw a re config u r a tion b it s th a t a ffect oper a tion a t the s y s tem level. the s e c a n b e ch a nged b y the a pplic a tion s oftw a re bu t a re s et to their def au lt v a l u e s u pon a ny re s et. mo s t peripher a l s a l s o h a ve m u ltiple config u r a tion b it s th a t a re not li s ted here. table 2-1. u s er config u r a tion f us e s fuse name description clock so u rce a select s b etween the high speed cry s t a l o s cill a tor, low power cry s t a l o s cill a tor, extern a l clock on xtal1a or intern a l rc o s cill a tor for the s o u rce of the s y s tem clock when o s cill a tor a i s s elected. clock so u rce b select s b etween the 32 khzcry s t a l o s cill a tor, extern a l clock on xtal1b or intern a l rc o s cill a tor for the s o u rce of the s y s tem clock when o s cill a tor b i s s elected (at 8 9lp51id2 only). o s cill a tor select select s whether o s cill a tor a or b i s en ab led to b oot the device. (at 8 9lp51id2 only) x2 mode select s the def au lt s t a te of whether the clock s o u rce i s divided b y two (x1) or not (x2) to gener a te the s y s tem clock. st a rt- u p time select s time-o u t del a y for the por/bod/pwd w a ke- u p period. comp a ti b ility mode config u re s the cpu in 12-clock comp a ti b ility or s ingle-cycle f as t exec u tion mode. xram config u r a tion config u re s if a cce ss to on-chip memorie s th a t a re m a pped to the extern a l d a t a memory a ddre ss s p a ce i s en ab led/di sab led b y def au lt. bootlo a der j u mp bit en ab le s or di sab le s the on- s hip b ootlo a der. on-chip de bu g en ab le en ab le s or di sab le s on-chip de bu g. ocd m us t b e en ab led prior to us ing a n in-circ u it de bu gger with the device. in-sy s tem progr a mming en ab le en ab le s or di sab le s in-sy s tem progr a mming. u s er sign a t u re progr a mming en ab le en ab le s or di sab le s progr a mming of u s er sign a t u re a rr a y. def au lt port st a te config u re s the def au lt port s t a te as inp u t-only mode (tri s t a ted) or q uas i- b idirection a l mode (we a kly p u lled high). low power mode en ab le s or di sab le s power red u ction fe a t u re s for lower s y s tem freq u encie s . table 2-2. import a nt softw a re config u r a tion bit s bit(s) sfr location description pxm0.y pxm1.y p0m0, p0m1, p1m0, p1m1, p2m0, p2m1, p3m0, p3m1, p4m0, p4m1 config u re s the i/o mode of port x pin y to b e one of inp u t-only, q uas i- b idirection a l, p us h-p u ll o u tp u t or open-dr a in. the def au lt s t a te i s controlled b y the def au lt port st a te f us e ab ove ckrl ckrl select s the divi s ion r a tio b etween the o s cill a tor a nd the s y s tem clock tps 3-0 clkreg.7-4 select s the divi s ion r a tio b etween the s y s tem clock a nd the timer s ales auxr.0 en ab le s /di sab le s toggling of ale exram auxr.1 en ab le s /di sab le s a cce ss to on-chip memorie s th a t a re m a pped to the extern a l d a t a memory a ddre ss s p a ce ws 1-0 auxr.6-5 select s the n u m b er of w a it s t a te s when a cce ss ing extern a l d a t a memory xstk auxr1.4 config u re s the h a rdw a re s t a ck to b e in ram or extr a ram eee eecon.1 en ab le s /di sab le s a cce ss to the on-chip eeprom enboot auxr1.5 en ab le s /di sab le s a cce ss to the on-chip fl as h api
9 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 2.3 comparison to the atmel at89c51rd2/ed2/id2 the atmel ? at 8 9lp51rd2/ed2/id2 i s p a rt of a f a mily of device s with enh a nced fe a t u re s th a t a re f u lly b in a ry comp a ti b le with the 8 051 in s tr u ction s et. the at 8 9lp51rd2/ed2/id2 h as two mode s of oper a tion s , comp a ti b ility mode a nd f as t mode. in comp a ti b ility mode the in s tr u ction timing, peripher a l b eh a vior, sfr a ddre ss e s , b it ass ignment s a nd pin f u nction s a re identic a l to the exi s ting atmel at 8 9c51rd2/ed2/id2 prod u ct. addition a l enh a ncement s a re tr a n s p a rent to the us er a nd c a n b e us ed if de s ired. f as t mode a llow s gre a ter perform a nce, bu t with s ome dif- ference s in b eh a vior. the m a jor enh a ncement s from the at 8 9c51rd2/ed2/id2 a re o u tlined in the following p a r a gr a ph s a nd m a y b e us ef u l to us er s migr a ting to the at 8 9lp51rd2/ed2/id2 from older device s . a su mm a ry of the difference s b etween comp a ti b ility a nd f as t mode s i s given in t ab le 2-3 on p a ge 11 . see a l s o the applic a tion note ?migr a ting from at 8 9c51rd2/ed2/id2 to at 8 9lp51rd2/ed2/id2.? 2.3.1 instruction execution in comp a ti b ility mode the atmel ? at 8 9lp51rd2/ed2/id2 cpu us e s the s ix- s t a te m a chine cycle of the s t a nd a rd 8 051 where in s tr u ction b yte s a re fetched every three s y s tem clock cycle s . exec u tion time s in thi s mode a re identic a l to the atmel at 8 9c51rd2/ed2/id2. for gre a ter per- form a nce the us er c a n en ab le f as t mode b y di sab ling the comp a ti b ility f us e. in f as t mode the cpu fetche s one code b yte from memory every clock cycle in s te a d of every three clock cycle s . thi s gre a tly incre as e s the thro u ghp u t of the cpu. e a ch s t a nd a rd in s tr u ction exec u te s in only one to fo u r clock cycle s . see d a t as heet for more det a il s . any s oftw a re del a y loop s or in s tr u ction- bas ed timing oper a tion s m a y need to b e ret u ned to a chieve the de s ired re su lt s in f as t mode. 2.3.2 system clock the s y s tem clock s o u rce i s not limited to a cry s t a l or extern a l clock. the s y s tem clock s o u rce i s s elect ab le b etween the cry s t a l o s cill a tor, a n extern a lly driven clock a nd a n intern a l 8 .0mhz rc o s cill a tor for at 8 9lp51rd2/ed2 a nd clock s o u rce a of at 8 9lp51id2. clock s o u rce b of at 8 9lp51id2 i s not limited to a 32 khz cry s t a l. the clock s o u rce b i s s elect ab le b etween the 32 khz cry s t a l o s cill a tor, a n extern a lly driven clock a nd a n intern a l 8 .0mhz rc o s cill a tor. unlike at 8 9c51id2, the x2 a nd ckrl fe a t u re s will a l s o a ffect the oscb s o u rce. by def au lt in comp a ti b ility mode the s y s tem clock freq u ency i s divided b y 2 from the extern a lly su pplied xtal1 freq u ency for comp a ti b ility with s t a nd a rd 8 051 s (12 clock s per m a chine cycle). the sy s tem clock divider c a n s c a le the s y s tem clock ver sus the o s cill a tor s o u rce. the divide- b y-2 c a n b e di sab led to oper a te in x2 mode (6 clock s per m a chine cycle) or the clock m a y b e f u rther divided to red u ce the oper a ting freq u ency. in f as t mode the clock divider def au lt s to divide b y 1. 2.3.3 reset the rst pin of the at 8 9lp51rd2/ed2/id2 h as s elect ab le pol a rity us ing the pol pin (formerly ea ). when pol i s high the rst pin i s a ctive high with a p u ll-down re s i s tor a nd when pol i s low the rst pin i s a ctive low with a p u ll- u p re s i s tor. for exi s ting at 8 9c51rd2/ed2/id2 s ocket s where ea i s tied to vdd, repl a cing at 8 9c51rd2/ed2 with at 8 9lp51rd2/ed2/id2 will m a in- t a in the a ctive high re s et. note th a t forcing extern a l exec u tion b y tying ea low i s not su pported. the at 8 9lp51rd2/ed2/id2 incl u de s a n on-chip power-on re s et a nd brown-o u t detector cir- c u it th a t en su re s th a t the device i s re s et from s y s tem power u p. in mo s t c as e s a rc s t a rt u p circ u it i s not req u ired on the rst pin, red u cing s y s tem co s t, a nd the rst pin m a y b e left u ncon- nected if a b o a rd-level re s et i s not pre s ent.
10 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 2.3.4 timer/counters a common pre s c a ler i s a v a il ab le to divide the time bas e for timer 0, timer 1, timer 2 a nd the wdt. the tps 3-0 b it s in the clkreg sfr control the pre s c a ler. in comp a ti b ility mode tps 3-0 def au lt s to 0101b, which c aus e s the timer s to co u nt once every m a chine cycle. the co u nting r a te c a n b e a dj us ted line a rly from the s y s tem clock r a te to 1/16 of the s y s tem clock r a te b y ch a nging tps 3-0 . in f as t mode tps 3-0 def au lt s to 0000b, or the s y s tem clock r a te. tps doe s not a ffect timer 2 in clock o u t or b au d gener a tor mode s . in comp a ti b ility mode the sa mpling of the extern a l timer/co u nter pin s : t0, t1, t2 a nd t2ex; a nd the extern a l interr u pt pin s , int0 a nd int1 , i s a l s o controlled b y the pre s c a ler. in f as t mode the s e pin s a re a lw a y s sa mpled a t the s y s tem clock r a te. both timer 0 a nd timer 1 c a n toggle their re s pective co u nter pin s , t0 a nd t1, when they over- flow b y s etting the o u tp u t en ab le b it s in tconb. 2.3.5 interrupt handling f as t mode a llow s for f as ter interr u pt re s pon s e d u e to the s horter in s tr u ction exec u tion time s . 2.3.6 keyboard interface the at 8 9lp51rd2/ed2/id2 doe s not cle a r the key b o a rd fl a g regi s ter (kbf) a fter a re a d. e a ch b it m us t b e cle a red in s oftw a re. thi s a llow s the interr u pt to b e gener a te once per fl a g when m u l- tiple fl a g s a re s et, if de s ired. to mimic the old b eh a vior the s ervice ro u tine m us t cle a r the whole regi s ter. the key b o a rd c a n a l s o su pport gener a l edge-triggered interr u pt s with the a ddition of the kbmod regi s ter. 2.3.7 serial port the timer pre s c a ler incre as e s the r a nge of a chiev ab le bau d r a te s when us ing timer 1 to gener- a te the bau d r a te in uart mode s 1 or 3, incl u ding a n incre as e in the m a xim u m bau d r a te a v a il ab le in comp a ti b ility mode. addition a l fe a t u re s incl u de au tom a tic a ddre ss recognition a nd fr a ming error detection. the s hift regi s ter mode (mode 0) h as b een enh a nced with more control of the pol a rity, ph as e a nd freq u ency of the clock a nd f u ll-d u plex oper a tion. thi s a llow s em u l a tion of m as ter s eri a l peripher a l (spi) a nd two-wire (twi) interf a ce s . 2.3.8 i/o ports the p0, p1, p2 a nd p3 i/o port s of the at 8 9lp51rd2/ed2/id2 m a y b e config u red in fo u r differ- ent mode s . the def au lt s etting depend s on the tri s t a te-port u s er f us e. when the f us e i s s et a ll the i/o port s revert to inp u t-only (tri s t a ted) mode a t power- u p or re s et. when the f us e i s not a ctive, port s p1, p2 a nd p3 s t a rt in q uas i- b idirection a l mode a nd p0 s t a rt s in open-dr a in mode. p4 a lw a y s oper a te s in q uas i- b idirection a l mode. p0 c a n b e config u red to h a ve intern a l p u ll- u p s b y pl a cing it in q uas i- b idirection a l or o u tp u t mode s . thi s c a n red u ce s y s tem co s t b y removing the need for extern a l p u ll- u p s on port 0. the p4.4?p4.7 pin s a re a ddition a l i/o s th a t repl a ce the norm a lly dedic a ted ale, psen, xtal1 a nd xtal2 pin s of the at 8 9c51rd2/ed2/id2. the s e pin s c a n b e us ed as a ddition a l i/o s depending on the config u r a tion of the clock a nd extern a l memory.
11 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 2.3.9 security the at 8 9lp51rd2/ed2/id2 doe s not su pport the extern a l a cce ss pin (ea ). therefore it i s not po ss i b le to exec u te from extern a l progr a m memory in a ddre ss r a nge 0000h?1fffh. when the third lock b it i s en ab led (lock mode 4) extern a l progr a m exec u tion i s di sab led for a ll a ddre ss e s ab ove 1fffh. thi s differ s from at 8 9c51rd2/ed2/id2 where lock mode 4 prevent s ea from b eing sa mpled low, bu t m a y s till a llow extern a l exec u tion a t a ddre ss e s o u t s ide the 8 k intern a l s p a ce. 2.3.10 programming the at 8 9lp51rd2/ed2/id2 su pport s a richer comm a nd s et for in-sy s tem progr a mming (isp). exi s ting at 8 9c51rd2/ed2 progr a mmer s s ho u ld b e ab le to progr a m the at 8 9lp51rd2/ed2/id2 in b yte mode. in p a ge mode the at 8 9lp51rd2/ed2/id2 only su pport s progr a mming of a h a lf-p a ge of 64 b yte s a nd therefore req u ire s a n extr a a ddre ss b yte as com- p a red to at 8 9c51rd2/ed2. f u rthermore the device s ign a t u re i s loc a ted a t a ddre ss e s 0000h, 0001h a nd 0003h in s te a d of 0000h, 0100h a nd 0200h. table 2-3. comp a ti b ility mode ver sus f as t mode s u mm a ry feature compatibility fast in s tr u ction fetch in sy s tem clock s 31 in s tr u ction exec u tion time in sy s tem clock s 6, 12, 1 8 or 24 1, 2, 3, 4 or 5 def au lt sy s tem clock divi s or 2 1 def au lt timer pre s c a ler divi s or 6 1 pin s a mpling r a te (int0 , int1 , t0, t1, t2, t2ex) pre s c a ler r a te sy s tem clock minim u m rst inp u t p u l s e in sy s tem clock s 12 2
12 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 3. special function registers a m a p of the on-chip memory a re a c a lled the speci a l f u nction regi s ter (sfr) s p a ce i s s hown in t ab le 3-1 . note th a t not a ll of the a ddre ss e s a re occ u pied, a nd u nocc u pied a ddre ss e s m a y not b e imple- mented on the chip. re a d a cce ss e s to the s e a ddre ss e s will in gener a l ret u rn r a ndom d a t a , a nd write a cce ss e s will h a ve a n indetermin a te effect. u s er s oftw a re s ho u ld not write to the s e u nli s ted loc a tion s , s ince they m a y b e us ed in f u t u re prod u ct s to invoke new fe a t u re s . note s :1.all sfr s in the left-mo s t col u mn a re b it- a ddre ssab le. 2. re s et v a l u e i s 1111 1111b when tri s t a te-port f us e i s en ab led a nd 0000 0000b when di sab led. 3. re s et v a l u e i s 0101 0010b when comp a ti b ility mode i s en ab led a nd 0000 0000b when di sab led. table 3-1. atmel at 8 9lp51rd2/ed2/id2 sfr m a p a nd re s et v a l u e s 8 9abcdef 0f 8 h ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 0ffh 0f0h b 0000 0000 rl0 0000 0000 rl1 0000 0000 rh0 0000 0000 rh1 0000 0000 pag e 0000 0000 bx 0000 0000 0f7h 0e 8 h cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 spx xxxx x000 0efh 0e0h acc 0000 0000 ax 0000 0000 dspr 0000 0000 fird 0000 0000 macl 0000 0000 mach 0000 0000 p0m0 (2) p0m1 0000 0000 0e7h 0d 8 h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 0dfh 0d0h psw 0000 0000 fcon xxxx 0000 eecon 0000 0000 dplb 0000 0000 dphb 0000 0000 p1m0 (2) p1m1 0000 0000 0d7h 0c 8 ht2con 0000 0000 t2mod 0000 0000 rcap2l 0000 000 rcap2h 0000 0000 tl2 0000 000 th2 0000 0000 p2m0 (2) p2m1 0000 0000 0cfh 0c0h p4 1111 1111 spcon 0001 0100 spsta 0000 0000 spdat xxxx xxxx p3m0 (2) p3m1 0000 0000 0c7h 0b 8 h ipl0 xx00 0000 saden 0000 0000 aref 0000 0000 p4m0 (2) p4m1 0000 0000 0bfh 0b0h p3 1111 1111 ien1 xxxx 0000 ipl1 xxxx 0000 iph1 xxxx 0000 iph0 xx00 0000 0b7h 0a 8 h ien0 0x00 0000 saddr 0000 0000 acsrb 0000 0000 dadl 0000 0000 dadh 0000 0000 clkreg 0101 xxxx ckcon1 xxxx xxx0 0afh 0a0h p2 1111 1111 dpcf 0000 0000 auxr1 0000 00x0 acsra 0000 0000 dadc 0000 0000 dadi 0000 0000 wdtrst (write-only) wdtprg 0000 0xx0 0a7h 9 8 h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 kbls 0000 0000 kbe 0000 0000 kbf 0000 0000 kbmod 0000 0000 9fh 90h p1 1111 1111 tconb 0010 0100 bmsel xxxx xxx0 sscon 0000 0000 sscs 1111 1000 ssdat 1111 1111 ssadr 1111 1110 ckrl 1111 1111 97h 88 h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0000 0000 ckcon0 0000 0000 8 fh 8 0h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 cksel xxxx xxx0 osccon xxxx x001 pcon 000x 0000 8 7h 01234567
13 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary note: 1. pre s ent on at 8 9lp51id2 only table 3-2. c51 core sfr s mnemonicaddname 76543210 acc e0h acc u m u l a tor b f0h b regi s ter psw d0h progr a m st a t us word cy ac f0 rs1 rs0 ov f1 p sp 8 1h st a ck pointer spx efh extended st a ck pointer ????sp11sp10sp9sp 8 dpl 8 2h d a t a pointer low byte dph 8 3h d a t a pointer high byte dplb d4h altern a te d a t a pointer low byte dphb d5h altern a te d a t a pointer high byte pag e f 6 h e r a m p a ge regi s ter ???? table 3-3. digit a l sign a l proce ss ing sfr s mnemonicaddname 76543210 ax e1h extended acc u m u l a tor bx f7h extended b regi s ter dspr e2h dsp control regi s ter mrw1 mrw0 smlb smla cbe1 cbe0 mvcd dprb fird e3h fifo depth macl e4h mac low byte mach e5h mac high byte table 3-4. sy s tem m a n a gement sfr s mnemonicaddname 76543210 pcon 8 7h power control smod1 smod0 pwdex pof gf1 gf0 pd idl auxr 8 eh a u xili a ry regi s ter 0 dpu ws1 ws0/m0 xrs2 xrs1 xrs0 extram ao auxr1 a2h a u xili a ry regi s ter 1 ? ? enboot xstk gf3 0 ? dps dpcr a3h d a t a pointer config regi s ter dpu1 dpu0 dpd1 dpd0 ? ? ? ? ckrl 97h clock relo a d regi s ter ckckon0 8 fh clock control regi s ter 0 twix2 wdtx2 pcax2 six2 t2x2 t1x2 t0x2 x2 ckckon1 afh clock control regi s ter 1 ???????spix2 cksel (1) 8 5h clock selection regi s ter ???????cks clkreg aeh clock regi s ter tps3 tps2 tps1 tps0 ? ? ? ? osccon (1) 8 5h o s cill a tor control regi s ter ?????sclkt0o s cben o s caen
14 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary table 3-5. interr u pt sfr s mnemonicaddname 76543210 ien0 a 8 h interr u pt en ab le control 0 ea ec et2 es et1 ex1 et0 ex0 ien1 b1h interr u pt en ab le control 1 ? ? eadc ecmp ? espi etwi ekb iph0 b7h interr u pt priority control high 0 ip1d ppch pt2h phs pt1h px1h pt0h px0h ipl0 b 8 h interr u pt priority control low 0 ip0d ppcl pt2l pls pt1l px1l pt0l px0l iph1 b3h interr u pt priority control high 1 ip3d ? padl pcmpl ? spih ptwl pkbh ipl1 b2h interr u pt priority control low 1 ip2d ? padh pcmph ? spil ptwh pkbl table 3-6. port sfr s mnemonicaddname 76543210 p0 8 0h 8 - b it port 0 p1 90h 8 - b it port 1 p2 a0h 8 - b it port 2 p3 b0h 8 - b it port 3 p4 c0h 8 - b it port 4 p0m0 e6h port 0 mode 0 p0m1 e7h port 0 mode 1 p1m0 d6h port 1 mode 0 p1m1 d7h port 1 mode 1 p2m0 ceh port 2 mode 0 p2m1 cfh port 2 mode 1 p3m0 c6h port 3 mode 0 p3m1 c7h port 3 mode 1 p4m0 beh port 4 mode 0 p4m1 bfh port 4 mode 1 table 3-7. seri a l i/o port sfr s mnemonicaddname 76543210 scon 9 8 hseri a l control fe/sm0 sm1 sm2 ren tb 8 rb 8 ti ri sbuf 99h seri a l d a t a b u ffer saden b9h sl a ve addre ss m as k saddr a9h sl a ve addre ss bdrcon 9bh b au d r a te control ? ? ? brr tbck rbck spd src brl 9ah b au d r a te relo a d
15 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary table 3-8. timer sfr s mnemonicaddname 76543210 tcon 88 htimer/co u nter 0 a nd 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 8 9h timer/co u nter 0 a nd 1 mode s gate1 c/t1 m11 m01 gate0 c/t0 m10 m00 tconb 91h timer/co u nter 0 a nd 1 mode b tl0 8 ah timer/co u nter 0 low byte th0 8 ch timer/co u nter 0 high byte tl1 8 bh timer/co u nter 1 low byte th1 8 dh timer/co u nter 1 high byte rl0 f2h timer/co u nter 0 relo a d low rh0 f3h timer/co u nter 0 relo a d high rtl1 f4h timer/co u nter 1 relo a d low rh1 f5h timer/co u nter 1 relo a d high wdtrst a6h w a tchdog timer re s et wdtprg a7h w a tchdog timer progr a m wto2wto1wto0 t2con c 8 htimer/co u nter 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 t2mod c9h timer/co u nter 2 mode ??????t2oedcen rcap2h cbh timer/co u nter 2 relo a d/c a pt u re high byte rcap2l cah timer/co u nter 2 relo a d/c a pt u re low byte th2 cdh timer/co u nter 2 high byte tl2 cch timer/co u nter 2 low byte table 3-9. spi controller sfr s mnemonicaddname 76543210 spcon c3h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spsta c4h spi st a t us spif wcol sserr modf spdat c5h spi d a t a spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 table 3-10. twi controller sfr s mnemonicaddname 76543210 sscon 93h synchrono us seri a l control sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 sscs 94h synchrono us seri a l st a t us ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0 ssdat 95h synchrono us seri a l d a t a ssadr 96h synchrono us seri a l addre ss ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssgc
16 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary table 3-11. key b o a rd interf a ce sfr s mnemonicaddname 76543210 kbls 9ch key b o a rd level selector kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 kbe 9dh key b o a rd inp u t en ab le kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 kbf 9eh key b o a rd fl a g regi s ter kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 kbmod 9fh key b o a rd mode regi s ter kbm7 kbm6 kbm5 kbm4 kbm3 kbm2 kbm1 kbm0 table 3-12. fl as h/eeprom memory sfr mnemonicaddname 76543210 bmsel 92h b a nk mode select regi s ter ???????fbs fcon d2h fl as h control regi s ter eee eebusy eecon d2h eeprom control regi s ter eee eebusy table 3-13. an a log comp a r a tor sfr s mnemonicaddname 76543210 acsra a3h comp a r a tor a control regi s ter acsrb abh comp a r a tor b control regi s ter aref bdh comp a r a tor reference regi s ter table 3-14. adc controller sfr s mnemonicaddname 76543210 dadc a4h dac/adc control regi s ter dadi a5h dac/adc inp u t regi s ter dadl ach dac/adc d a t a low regi s ter dadh adh dac/adc d a t a high regi s ter table 3-15. pca sfr s mnemo -nicaddname 76543210 ccon d 8 h pca timer/co u nter control cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod d9h pca timer/co u nter mode cidl wdte cps1 cps0 ecf cl e9h pca timer/co u nter low byte ch f9h pca timer/co u nter high byte ccapm0 dah pca timer/co u nter mode 0 ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 ccapm1 dbh pca timer/co u nter mode 1 ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 ccapm2 dch pca timer/co u nter mode 2 ecom2 capp2 capn2 mat2 tog2 pwm2 eccf2
17 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary ccapm3 ddh pca timer/co u nter mode 3 ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3 ccapm4 deh pca timer/co u nter mode 4 ecom4 capp4 capn4 mat4 tog4 pwm4 eccf4 ccap0h fah pca comp a re c a pt u re mod u le 0 h ccap0h7 ccap0h6 ccap0h5 ccap0h4 ccap0h3 ccap0h2 ccap0h1 ccap0h0 ccap1h fbh pca comp a re c a pt u re mod u le 1 h ccap1h7 ccap1h6 ccap1h5 ccap1h4 ccap1h3 ccap1h2 ccap1h1 ccap1h0 ccap2h fch pca comp a re c a pt u re mod u le 2 h ccap2h7 ccap2h6 ccap2h5 ccap2h4 ccap2h3 ccap2h2 ccap2h1 ccap2h0 ccap3h fdh pca comp a re c a pt u re mod u le 3 h ccap3h7 ccap3h6 ccap3h5 ccap3h4 ccap3h3 ccap3h2 ccap3h1 ccap3h0 ccap4h feh pca comp a re c a pt u re mod u le 4 h ccap4h7 ccap4h6 ccap4h5 ccap4h4 ccap4h3 ccap4h2 ccap4h1 ccap4h0 ccap0l eah pca comp a re c a pt u re mod u le 0 l ccap0l7 ccap0l6 ccap0l5 ccap0l4 ccap0l3 ccap0l2 ccap0l1 ccap0l0 ccap1l ebh pca comp a re c a pt u re mod u le 1 l ccap1l7 ccap1l6 ccap1l5 ccap1l4 ccap1l3 ccap1l2 ccap1l1 ccap1l0 ccap2l ech pca comp a re c a pt u re mod u le 2 l ccap2l7 ccap2l6 ccap2l5 ccap2l4 ccap2l3 ccap2l2 ccap2l1 ccap2l0 ccap3l edh pca comp a re c a pt u re mod u le 3 l ccap3l7 ccap3l6 ccap3l5 ccap3l4 ccap3l3 ccap3l2 ccap3l1 ccap3l0 ccap4l eeh pca comp a re c a pt u re mod u le 4 l ccap4l7 ccap4l6 ccap4l5 ccap4l4 ccap4l3 ccap4l2 ccap4l1 ccap4l0 table 3-15. pca sfr s (contin u ed) mnemo -nicaddname 76543210
18 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 4. ordering information note s : 1. speed i s s pecified for s ingle-cycle f as t mode with x2 clock 2. see t ab le 4-1 on p a ge 19 for a cro ss reference b etween at 8 9c51rd2/ed2/id2 a nd at 8 9lp51rd2/ed2/id2 4.1 green package op tion (pb/halide-free) supply voltage speed (1) temperature range data eeprom # oscillators ordering code package packing 2.4v to 5.5v 20 mhz ind us tri a l (-40 c to 8 5 c) no 1 at 8 9lp51rd2-20aau 44aa (lqfp) tr a y at 8 9lp51rd2-20aaur reel at 8 9lp51rd2-20au 44a (tqfp) tr a y at 8 9lp51rd2-20aur reel at 8 9lp51rd2-20ju 44j (plcc) stick at 8 9lp51rd2-20jur reel at 8 9lp51rd2-20mu 44m1 (vqfn) tr a y at 8 9lp51rd2-20mur reel at 8 9lp51rd2-20pu 40p6 (pdip) stick ye s 1 at 8 9lp51ed2-20aau 44aa (lqfp) tr a y at 8 9lp51ed2-20aaur reel at 8 9lp51ed2-20au 44a (tqfp) tr a y at 8 9lp51ed2-20aur reel at 8 9lp51ed2-20ju 44j (plcc) stick at 8 9lp51ed2-20jur reel at 8 9lp51ed2-20mu 44m1 (vqfn) tr a y at 8 9lp51ed2-20mur reel at 8 9lp51ed2-20pu 40p6 (pdip) stick ye s 2 at 8 9lp51id2-20aau 44aa (lqfp) tr a y at 8 9lp51id2-20aaur reel at 8 9lp51id2-20au 44a (tqfp) tr a y at 8 9lp51id2-20aur reel at 8 9lp51id2-20ju 44j (plcc) stick at 8 9lp51id2-20jur reel at 8 9lp51id2-20mu 44m1 (vqfn) tr a y package types 44aa 44-le a d, very thin pl as tic q ua d fl a t p a ck a ge, 1.2 mm thickne ss (vqfp/lqfp) 44a 44-le a d, thin pl as tic q ua d fl a t p a ck a ge, 1.0 mm thickne ss (tqfp) 44j 44-le a d, pl as tic j-le a ded chip c a rrier (plcc) 44m1 44-p a d, 7 x 7 x 1.0 mm body, pl as tic very thin q ua d fl a t no le a d p a ck a ge (vqfn/mlf) 40p6 40-le a d, 0.600? wide, pl as tic d ua l inline p a ck a ge (pdip)
19 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 4.2 cross reference wi th at89c51rd2/ed2/id2 table 4-1. ordering cro ss reference at 8 9c51rd2/ed2/id2 to at 8 9lp51rd2/ed2/id2 device migration package packing previous ordering code new ordering code at 8 9c51rd2 to at 8 9lp51rd2 plcc44 stick at 8 9c51rd2-slsum at 8 9lp51rd2-20ju reel at 8 9c51rd2-slrum at 8 9lp51rd2-20jur vqfp44 tr a yat 8 9c51rd2-rltum at 8 9lp51rd2-20aau reel at 8 9c51rd2-rlrum at 8 9lp51rd2-20aaur at 8 9c51ed2 to at 8 9lp51ed2 plcc44 stick at 8 9c51ed2-slsum at 8 9lp51ed2-20ju reel at 8 9c51ed2-slrum at 8 9lp51ed2-20jur vqfp44 tr a yat 8 9c51ed2-rltum at 8 9lp51ed2-20aau reel at 8 9c51ed2-rlrum at 8 9lp51ed2-20aaur at 8 9c51id2 to at 8 9lp51id2 plcc44 stick at 8 9c51id2-slsum at 8 9lp51id2-20ju reel at 8 9c51id2-slrum at 8 9lp51id2-20jur vqfp44 tr a yat 8 9c51id2-rltum at 8 9lp51id2-20aau reel at 8 9c51id2-rlrum at 8 9lp51id2-20aaur table 4-2. p a ck a ge s not fo u nd in at 8 9c51rd2/ed2/id2 device package packing ordering code at 8 9c51rd2 to at 8 9lp51rd2 pdip40 stick at 8 9lp51rd2-20pu tqfp44 tr a yat 8 9lp51rd2-20au reel at 8 9lp51rd2-20aur vqfn44 tr a yat 8 9lp51rd2-20mu reel at 8 9lp51rd2-20mur at 8 9c51ed2 to at 8 9lp51ed2 pdip40 stick at 8 9lp51ed2-20pu tqfp44 tr a yat 8 9lp51ed2-20au reel at 8 9lp51ed2-20aur vqfn44 tr a yat 8 9lp51ed2-20mu reel at 8 9lp51ed2-20mur at 8 9c51id2 to at 8 9lp51id2 pdip40 stick at 8 9lp51id2-20pu tqfp44 tr a yat 8 9lp51id2-20au reel at 8 9lp51id2-20aur vqfn44 tr a yat 8 9lp51id2-20mu reel at 8 9lp51id2-20mur
20 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 5. packaging information 5.1 44aa ? vqfp/lqfp 2 3 25 orchard parkway s an jose, ca 951 3 1 title drawing no. r rev. 44aa, 44-lead, 10 x 10 mm body s ize, 1.4 mm body thickness, 0.8 mm lead pitch, low profile plastic quad flat package (vqfp) b 44aa 10/5/2001 pin 1 identifier 0~8 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1. this package conforms to jedec reference m s -026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3 . lead coplanarity is 0.102 mm maximum. a ? ? 1.60 a1 0.05 ? 0.15 a2 0.95 1.40 1.05 d 11.9 12.00 12.10 d1 9.90 10.00 10.10 note 2 e 11.9 12.00 12.10 e1 9.90 10.00 10.10 note 2 b 0. 3 0 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
21 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 5.2 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
22 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 5.3 44j ? plcc note s : 1. thi s p a ck a ge conform s to jedec reference ms-01 8 , v a ri a tion ac. 2. dimen s ion s d1 a nd e1 do not incl u de mold protr us ion. allow ab le protr us ion i s .010"(0.254 mm) per s ide. dimen s ion d1 a nd e1 incl u de mold mi s m a tch a nd a re me asu red a t the extreme m a teri a l condition a t the u pper or lower p a rting line. 3. le a d copl a n a rity i s 0.004" (0.102 mm) m a xim u m. a 4.191 ? 4.572 a1 2.2 8 6 ? 3.04 8 a2 0.50 8 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.9 8 6 ? 16.002 b 0.660 ? 0. 8 13 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of me asu re = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.31 8 (0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-le a d, pl as tic j-le a ded chip c a rrier (plcc) b 44j 10/04/01 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev.
23 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 5.4 44m1 ? vqfn/mlf title drawing no. gpc rev. packa g e drawin g contact: packagedrawings@atmel.com 44m1 zw s h 44m1, 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, 5.20 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 9/26/08 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a 3 0.20 ref b 0.18 0.2 3 0. 3 0 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 b s c l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec s tandard mo-220, fig. 1 ( s aw s ingulation) vkkd- 3 . top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a 3 a s eating plane pin #1 triangle pin #1 chamfer (c 0. 3 0) option a option b pin #1 notch (0.20 r) option c k k 1 2 3
24 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 5.5 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 52.070 52.578 note 2 e 15.240 15.875 e1 13.462 13.970 note 2 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
25 3714as?micro?7/11 at89lp51rd2/ed2/id2 summary - preliminary 6. revision history revision no. history revi s ion a ? j u ly 2011 ? initi a l rele as e
3714as?micro?7/11 atmel corporation 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 usa tel : (+1) (40 8 ) 441-0311 fax : (+1) (40 8 ) 4 8 7-2600 www. a tmel.com 8 051@ a tmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millenni u m city 5 41 8 kw u n tong ro a d kw u n tong, kowloon hong kong tel : (+ 8 52) 2245-6100 fax : (+ 8 52) 2722-1369 atmel munich gmbh b us ine ss c a mp us p a ckring 4 d- 8 574 8 g a rching b . m u nich germany tel : (+49) 8 9-31970-0 fax : (+49) 8 9-3194621 atmel japan 9f, tonet su shink a w a bldg. 1-24- 8 shink a w a ch u o-k u , tokyo 104-0033 japan tel : (+ 8 1) (3) 3523-3551 fax : (+ 8 1)( 3) 3523-75 8 1 di s cl a imer: the inform a tion in thi s doc u ment i s provided in connection with atmel prod u ct s . no licen s e, expre ss or implied, b y e s toppel or otherwi s e, to a ny intellect ua lproperty right i s gr a nted b y thi s doc u ment or in connection with the sa le of atmel prod u ct s . except as set forth in atmel?s terms and conditions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied war- ranty of merchantability, fitness for a partic ular purpose, or non-infringement. in no event shall atmel be liable for any dire ct, indirect, consequential, punitive, special or incidental damages (i ncluding, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel m a ke s no repre s ent a tion s or w a rr a ntie s with re s pect to the a cc u r a cy or completene ss of the content s of thi s doc u ment a nd re s erve s the right to m a ke ch a nge s to s pecific a tion s a nd prod u ct de s cription s a t a ny time witho u t notice. atmel doe s not m a ke a ny commitment to u pd a te the inform a tion cont a ined herein. unle ss s pecific a lly provided otherwi s e, atmel prod u ct s a re not su it ab le for, a nd s h a ll not b e us ed in, au tomotive a pplic a tion s . atmel? s prod u ct s a re not intended, au thorized, or w a rr a nted for us e as component s in a pplic a tion s intended to su pport or sus t a in life. ? 2011 atmel corpor a tion. all right s re s erved. atmel ? , atmel logo a nd com b in a tion s thereof, a nd other s a re regi s tered tr a dem a rk s or tr a dem a rk s of atmel corpor a tion or it s subs idi a rie s . other term s a nd prod u ct n a me s m a y b e tr a dem a rk s of other s .

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